Timing Report

Need help reading this report?

Design Name TIGARI_CTRL
Device, Speed (SpeedFile Version) XC9572XL, -10 (3.0)
Date Created Sat Aug 15 22:39:39 2020
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'CE_WE_IC2.CLKF' has multiple original clock nets 'XLXN_104.Q' 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN'.
Possible asynchronous logic: Clock pin 'CE_WE_IC1.CLKF' has multiple original clock nets 'XLXN_92.Q' 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN'.
Possible asynchronous logic: Clock pin 'AUDCTL1.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN' 'Atari_A0' 'Atari_A1' 'Atari_A2'.
Possible asynchronous logic: Clock pin 'AUDCTL2.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN' 'Atari_A0' 'Atari_A1' 'Atari_A2'.
Possible asynchronous logic: Clock pin 'XLXN_104.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN' 'Atari_A0' 'Atari_A1' 'Atari_A2'.
Possible asynchronous logic: Clock pin 'XLXN_92.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN' 'Atari_A0' 'Atari_A1' 'Atari_A2'.
Possible asynchronous logic: Clock pin 'DATA_INTERNAL<0>.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN'.
Possible asynchronous logic: Clock pin 'DATA_INTERNAL<1>.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN'.
Possible asynchronous logic: Clock pin 'DATA_INTERNAL<2>.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN'.
Possible asynchronous logic: Clock pin 'DATA_INTERNAL<3>.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN'.
Possible asynchronous logic: Clock pin 'DATA_INTERNAL<4>.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN'.
Possible asynchronous logic: Clock pin 'DATA_INTERNAL<5>.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN'.
Possible asynchronous logic: Clock pin 'DATA_INTERNAL<6>.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN'.
Possible asynchronous logic: Clock pin 'DATA_INTERNAL<7>.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN'.
Possible asynchronous logic: Clock pin 'NEG_AUDCTL1.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN' 'Atari_A0' 'Atari_A1' 'Atari_A2'.
Possible asynchronous logic: Clock pin 'NEG_AUDCTL2.CLKF' has multiple original clock nets 'Atari_PHI2' 'Atari_RW' 'CS_SELECT_IN' 'Atari_A0' 'Atari_A1' 'Atari_A2'.

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for XLXN_104.Q
Clock to Setup (tCYC) 10.000 ns.
Pad to Pad Delay (tPD) 11.000 ns.
Setup to Clock at the Pad (tSU) 2.100 ns.
Clock Pad to Output Pad Delay (tCO) 18.100 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
TS1006 0.0 0.0 0 0
TS1007 0.0 0.0 0 0
TS1008 0.0 0.0 0 0
TS1009 0.0 0.0 0 0
TS1010 0.0 0.0 0 0
AUTO_TS_F2F 0.0 10.0 3 3
AUTO_TS_P2P 0.0 18.1 144 144
AUTO_TS_P2F 0.0 8.3 79 79
AUTO_TS_F2P 0.0 4.0 16 16


Constraint: TS1000

Description: PERIOD:PERIOD_XLXN_104.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_XLXN_92.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_Ready_2:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_Ready_1:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_Atari_PHI2:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_Atari_RW:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1006

Description: PERIOD:PERIOD_CS_SELECT_IN:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1007

Description: PERIOD:PERIOD_Atari_A0:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1008

Description: PERIOD:PERIOD_Atari_A1:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1009

Description: PERIOD:PERIOD_Atari_A2:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1010

Description: PERIOD:PERIOD_GEN_IN:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
GEN_OUT_4.Q to OUT_HELPER1.D 0.000 10.000 -10.000
XLXI_99/Q0.Q to GEN_OUT_4.D 0.000 10.000 -10.000
XLXI_99/Q0.Q to OUT_HELPER1.D 0.000 10.000 -10.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Atari_A0 to CE_WE_IC1 0.000 18.100 -18.100
Atari_A0 to CE_WE_IC2 0.000 18.100 -18.100
Atari_A1 to CE_WE_IC1 0.000 18.100 -18.100


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
ATARI_DATA<0> to DATA_INTERNAL<0>.D 0.000 8.300 -8.300
ATARI_DATA<1> to DATA_INTERNAL<1>.D 0.000 8.300 -8.300
ATARI_DATA<2> to DATA_INTERNAL<2>.D 0.000 8.300 -8.300


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
AUDCTL1.Q to AUDCTL1 0.000 4.000 -4.000
AUDCTL2.Q to AUDCTL2 0.000 4.000 -4.000
CE_WE_IC1.Q to CE_WE_IC1 0.000 4.000 -4.000



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
XLXN_104.Q 71.429 Limited by Clock Pulse Width for XLXN_104.Q
XLXN_92.Q 71.429 Limited by Clock Pulse Width for XLXN_92.Q
Ready_2 71.429 Limited by Clock Pulse Width for Ready_2
Ready_1 71.429 Limited by Clock Pulse Width for Ready_1
Atari_PHI2 71.429 Limited by Clock Pulse Width for Atari_PHI2
Atari_RW 71.429 Limited by Clock Pulse Width for Atari_RW
CS_SELECT_IN 71.429 Limited by Clock Pulse Width for CS_SELECT_IN
Atari_A0 71.429 Limited by Clock Pulse Width for Atari_A0
Atari_A1 71.429 Limited by Clock Pulse Width for Atari_A1
Atari_A2 71.429 Limited by Clock Pulse Width for Atari_A2
GEN_IN 71.429 Limited by Clock Pulse Width for GEN_IN

Setup/Hold Times for Clocks

Setup/Hold Times for Clock Atari_PHI2
Source Pad Setup to clk (edge) Hold to clk (edge)
ATARI_DATA<0> 2.100 1.400
ATARI_DATA<1> 2.100 1.400
ATARI_DATA<2> 2.100 1.400
ATARI_DATA<3> 2.100 1.400
ATARI_DATA<4> 2.100 1.400
ATARI_DATA<5> 2.100 1.400
ATARI_DATA<6> 2.100 1.400
ATARI_DATA<7> 2.100 1.400

Setup/Hold Times for Clock Atari_RW
Source Pad Setup to clk (edge) Hold to clk (edge)
ATARI_DATA<0> 2.100 1.400
ATARI_DATA<1> 2.100 1.400
ATARI_DATA<2> 2.100 1.400
ATARI_DATA<3> 2.100 1.400
ATARI_DATA<4> 2.100 1.400
ATARI_DATA<5> 2.100 1.400
ATARI_DATA<6> 2.100 1.400
ATARI_DATA<7> 2.100 1.400

Setup/Hold Times for Clock CS_SELECT_IN
Source Pad Setup to clk (edge) Hold to clk (edge)
ATARI_DATA<0> 2.100 1.400
ATARI_DATA<1> 2.100 1.400
ATARI_DATA<2> 2.100 1.400
ATARI_DATA<3> 2.100 1.400
ATARI_DATA<4> 2.100 1.400
ATARI_DATA<5> 2.100 1.400
ATARI_DATA<6> 2.100 1.400
ATARI_DATA<7> 2.100 1.400


Clock to Pad Timing

Clock Atari_PHI2 to Pad
Destination Pad Clock (edge) to Pad
CE_WE_IC1 18.100
CE_WE_IC2 18.100
AUDCTL1 10.200
AUDCTL2 10.200
DATA_INTERNAL<0> 10.200
DATA_INTERNAL<1> 10.200
DATA_INTERNAL<2> 10.200
DATA_INTERNAL<3> 10.200
DATA_INTERNAL<4> 10.200
DATA_INTERNAL<5> 10.200
DATA_INTERNAL<6> 10.200
DATA_INTERNAL<7> 10.200
NEG_AUDCTL1 10.200
NEG_AUDCTL2 10.200

Clock Atari_RW to Pad
Destination Pad Clock (edge) to Pad
CE_WE_IC1 18.100
CE_WE_IC2 18.100
AUDCTL1 10.200
AUDCTL2 10.200
DATA_INTERNAL<0> 10.200
DATA_INTERNAL<1> 10.200
DATA_INTERNAL<2> 10.200
DATA_INTERNAL<3> 10.200
DATA_INTERNAL<4> 10.200
DATA_INTERNAL<5> 10.200
DATA_INTERNAL<6> 10.200
DATA_INTERNAL<7> 10.200
NEG_AUDCTL1 10.200
NEG_AUDCTL2 10.200

Clock CS_SELECT_IN to Pad
Destination Pad Clock (edge) to Pad
CE_WE_IC1 18.100
CE_WE_IC2 18.100
AUDCTL1 10.200
AUDCTL2 10.200
DATA_INTERNAL<0> 10.200
DATA_INTERNAL<1> 10.200
DATA_INTERNAL<2> 10.200
DATA_INTERNAL<3> 10.200
DATA_INTERNAL<4> 10.200
DATA_INTERNAL<5> 10.200
DATA_INTERNAL<6> 10.200
DATA_INTERNAL<7> 10.200
NEG_AUDCTL1 10.200
NEG_AUDCTL2 10.200

Clock Atari_A0 to Pad
Destination Pad Clock (edge) to Pad
CE_WE_IC1 18.100
CE_WE_IC2 18.100
AUDCTL1 10.200
AUDCTL2 10.200
NEG_AUDCTL1 10.200
NEG_AUDCTL2 10.200

Clock Atari_A1 to Pad
Destination Pad Clock (edge) to Pad
CE_WE_IC1 18.100
CE_WE_IC2 18.100
AUDCTL1 10.200
AUDCTL2 10.200
NEG_AUDCTL1 10.200
NEG_AUDCTL2 10.200

Clock Atari_A2 to Pad
Destination Pad Clock (edge) to Pad
CE_WE_IC1 18.100
CE_WE_IC2 18.100
AUDCTL1 10.200
AUDCTL2 10.200
NEG_AUDCTL1 10.200
NEG_AUDCTL2 10.200

Clock GEN_IN to Pad
Destination Pad Clock (edge) to Pad
GEN_OUT_4 10.200
OUT_HELPER1 10.200


Clock to Setup Times for Clocks

Clock to Setup for clock GEN_IN
Source Destination Delay
GEN_OUT_4.Q OUT_HELPER1.D 10.000
XLXI_99/Q0.Q GEN_OUT_4.D 10.000
XLXI_99/Q0.Q OUT_HELPER1.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
Atari_A0 ATARI_DATA<0> 11.000
Atari_A0 ATARI_DATA<1> 11.000
Atari_A0 ATARI_DATA<2> 11.000
Atari_A0 ATARI_DATA<3> 11.000
Atari_A0 ATARI_DATA<4> 11.000
Atari_A0 ATARI_DATA<5> 11.000
Atari_A0 ATARI_DATA<6> 11.000
Atari_A0 ATARI_DATA<7> 11.000
Atari_A1 ATARI_DATA<0> 11.000
Atari_A1 ATARI_DATA<1> 11.000
Atari_A1 ATARI_DATA<2> 11.000
Atari_A1 ATARI_DATA<3> 11.000
Atari_A1 ATARI_DATA<4> 11.000
Atari_A1 ATARI_DATA<5> 11.000
Atari_A1 ATARI_DATA<6> 11.000
Atari_A1 ATARI_DATA<7> 11.000
Atari_A2 ATARI_DATA<0> 11.000
Atari_A2 ATARI_DATA<1> 11.000
Atari_A2 ATARI_DATA<2> 11.000
Atari_A2 ATARI_DATA<3> 11.000
Atari_A2 ATARI_DATA<4> 11.000
Atari_A2 ATARI_DATA<5> 11.000
Atari_A2 ATARI_DATA<6> 11.000
Atari_A2 ATARI_DATA<7> 11.000
Atari_PHI2 ATARI_DATA<0> 11.000
Atari_PHI2 ATARI_DATA<1> 11.000
Atari_PHI2 ATARI_DATA<2> 11.000
Atari_PHI2 ATARI_DATA<3> 11.000
Atari_PHI2 ATARI_DATA<4> 11.000
Atari_PHI2 ATARI_DATA<5> 11.000
Atari_PHI2 ATARI_DATA<6> 11.000
Atari_PHI2 ATARI_DATA<7> 11.000
Atari_RW ATARI_DATA<0> 11.000
Atari_RW ATARI_DATA<1> 11.000
Atari_RW ATARI_DATA<2> 11.000
Atari_RW ATARI_DATA<3> 11.000
Atari_RW ATARI_DATA<4> 11.000
Atari_RW ATARI_DATA<5> 11.000
Atari_RW ATARI_DATA<6> 11.000
Atari_RW ATARI_DATA<7> 11.000
CS_SELECT_IN ATARI_DATA<0> 11.000
CS_SELECT_IN ATARI_DATA<1> 11.000
CS_SELECT_IN ATARI_DATA<2> 11.000
CS_SELECT_IN ATARI_DATA<3> 11.000
CS_SELECT_IN ATARI_DATA<4> 11.000
CS_SELECT_IN ATARI_DATA<5> 11.000
CS_SELECT_IN ATARI_DATA<6> 11.000
CS_SELECT_IN ATARI_DATA<7> 11.000
Atari_A5 D500 10.000
Atari_A5 D520 10.000
Atari_A5 D540 10.000
Atari_A5 D560 10.000
Atari_A5 D580 10.000
Atari_A5 D5A0 10.000
Atari_A5 D5C0 10.000
Atari_A5 D5E0 10.000
Atari_A6 D500 10.000
Atari_A6 D520 10.000
Atari_A6 D540 10.000
Atari_A6 D560 10.000
Atari_A6 D580 10.000
Atari_A6 D5A0 10.000
Atari_A6 D5C0 10.000
Atari_A6 D5E0 10.000
Atari_A7 D500 10.000
Atari_A7 D520 10.000
Atari_A7 D540 10.000
Atari_A7 D560 10.000
Atari_A7 D580 10.000
Atari_A7 D5A0 10.000
Atari_A7 D5C0 10.000
Atari_A7 D5E0 10.000
Atari_CCTL D500 10.000
Atari_CCTL D520 10.000
Atari_CCTL D540 10.000
Atari_CCTL D560 10.000
Atari_CCTL D580 10.000
Atari_CCTL D5A0 10.000
Atari_CCTL D5C0 10.000
Atari_CCTL D5E0 10.000
Ready_1 ATARI_DATA<6> 10.000
Ready_2 ATARI_DATA<7> 10.000



Number of paths analyzed: 242
Number of Timing errors: 242
Analysis Completed: Sat Aug 15 22:39:39 2020