********** Mapped Logic ********** |
BASE_negOE <= NOT (((PHI2 AND EXTSEL AND CAS_INH AND A15 AND R_W)
OR (PHI2 AND EXTSEL AND CAS_INH AND NOT A14 AND R_W) OR (MEM_SEL AND PB4 AND PHI2 AND EXTSEL AND CAS_INH AND R_W) OR (PB4 AND PHI2 AND EXTSEL AND CAS_INH AND XLXN_332 AND R_W) OR (NOT MEM_SEL AND PHI2 AND EXTSEL AND CAS_INH AND NOT XLXN_332 AND PB5 AND R_W))); |
BASE_negWE <= NOT (((PHI2 AND EXTSEL AND CAS_INH AND A15 AND NOT R_W)
OR (PHI2 AND EXTSEL AND CAS_INH AND NOT A14 AND NOT R_W) OR (MEM_SEL AND PB4 AND PHI2 AND EXTSEL AND CAS_INH AND NOT R_W) OR (PB4 AND PHI2 AND EXTSEL AND CAS_INH AND XLXN_332 AND NOT R_W) OR (NOT MEM_SEL AND PHI2 AND EXTSEL AND CAS_INH AND NOT XLXN_332 AND PB5 AND NOT R_W))); |
BAS_ENABLE <= NOT ((PB4 AND NOT PB1 AND PHI2 AND PB5)); |
FTCPE_DIV_CLK_IN: FTCPE port map (DIV_CLK_IN,'1',XLXN_401,'0','0'); |
EX_ADDR14 <= NOT (((NOT A14)
OR (MEM_SEL AND NOT PB4 AND NOT A15 AND NOT PB2) OR (NOT PB4 AND NOT A15 AND XLXN_332 AND NOT PB2) OR (NOT MEM_SEL AND NOT A15 AND NOT XLXN_332 AND NOT PB5 AND NOT PB2))); |
EX_ADDR15 <= ((A15)
OR (MEM_SEL AND NOT PB4 AND A14 AND PB3) OR (NOT PB4 AND A14 AND XLXN_332 AND PB3) OR (NOT MEM_SEL AND A14 AND NOT XLXN_332 AND NOT PB5 AND PB3)); |
EX_ADDR16 <= ((MEM_SEL AND NOT PB4 AND NOT A15 AND A14 AND PB6)
OR (NOT PB4 AND NOT A15 AND A14 AND XLXN_332 AND PB6) OR (NOT MEM_SEL AND NOT A15 AND A14 AND NOT XLXN_332 AND NOT PB5 AND PB6)); |
EX_ADDR17 <= ((MEM_SEL AND NOT PB4 AND PB7 AND NOT A15 AND A14)
OR (NOT PB4 AND PB7 AND NOT A15 AND A14 AND XLXN_332) OR (NOT MEM_SEL AND PB7 AND NOT A15 AND A14 AND NOT XLXN_332 AND NOT PB5)); |
EX_ADDR18 <= ((MEM_SEL AND NOT PB4 AND PB1 AND NOT A15 AND A14)
OR (NOT PB4 AND PB1 AND NOT A15 AND A14 AND XLXN_332) OR (NOT MEM_SEL AND PB1 AND NOT A15 AND A14 AND NOT XLXN_332 AND NOT PB5)); |
EX_ADDR19_TO_RAM1CSneg <= NOT ((MEM_SEL AND NOT PB4 AND NOT A15 AND A14 AND PB5)); |
EX_ADDR19_TO_RAM2CS_neg <= (MEM_SEL AND NOT PB4 AND NOT A15 AND A14 AND PB5); |
EX_negOE <= NOT (((MEM_SEL AND NOT PB4 AND PHI2 AND EXTSEL AND CAS_INH AND NOT A15 AND
A14 AND R_W) OR (NOT PB4 AND PHI2 AND EXTSEL AND CAS_INH AND NOT A15 AND A14 AND XLXN_332 AND R_W) OR (NOT MEM_SEL AND PHI2 AND EXTSEL AND CAS_INH AND NOT A15 AND A14 AND NOT XLXN_332 AND NOT PB5 AND R_W))); |
EX_negWE <= NOT (((MEM_SEL AND NOT PB4 AND PHI2 AND EXTSEL AND CAS_INH AND NOT A15 AND
A14 AND NOT R_W) OR (NOT PB4 AND PHI2 AND EXTSEL AND CAS_INH AND NOT A15 AND A14 AND XLXN_332 AND NOT R_W) OR (NOT MEM_SEL AND PHI2 AND EXTSEL AND CAS_INH AND NOT A15 AND A14 AND NOT XLXN_332 AND NOT PB5 AND NOT R_W))); |
MAP_SELFTEST <= NOT ((PB4 AND NOT PB7 AND PHI2 AND PB5)); |
FDCPE_XLXN_332: FDCPE port map (XLXN_332,HALT,NOT PHI2,'0','0'); |
FTCPE_XLXN_401: FTCPE port map (XLXN_401,'1',CLK_IN,'0','0'); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |