Timing Report

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Design Name acsi_cf
Device, Speed (SpeedFile Version) XC9536XL, -10 (3.0)
Date Created Thu Jul 30 16:56:57 2020
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'data_out<7>.CLKF' has multiple original clock nets 'i1_A1' 'i2_CS' 'i3_RW' 'i9_RESET'.
Possible asynchronous logic: Clock pin 'data_out<5>.CLKF' has multiple original clock nets 'i1_A1' 'i2_CS' 'i3_RW' 'i9_RESET'.
Possible asynchronous logic: Clock pin 'data_out<6>.CLKF' has multiple original clock nets 'i1_A1' 'i2_CS' 'i3_RW' 'i9_RESET'.
Possible asynchronous logic: Clock pin 'data_out<0>.CLKF' has multiple original clock nets 'i1_A1' 'i2_CS' 'i3_RW' 'i9_RESET'.
Possible asynchronous logic: Clock pin 'data_out<1>.CLKF' has multiple original clock nets 'i1_A1' 'i2_CS' 'i3_RW' 'i9_RESET'.
Possible asynchronous logic: Clock pin 'data_out<2>.CLKF' has multiple original clock nets 'i1_A1' 'i2_CS' 'i3_RW' 'i9_RESET'.
Possible asynchronous logic: Clock pin 'data_out<3>.CLKF' has multiple original clock nets 'i1_A1' 'i2_CS' 'i3_RW' 'i9_RESET'.
Possible asynchronous logic: Clock pin 'data_out<4>.CLKF' has multiple original clock nets 'i1_A1' 'i2_CS' 'i3_RW' 'i9_RESET'.

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for i1_A1
Pad to Pad Delay (tPD) 10.000 ns.
Setup to Clock at the Pad (tSU) 2.100 ns.
Clock Pad to Output Pad Delay (tCO) 17.900 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
AUTO_TS_F2F 0.0 0.0 0 0
AUTO_TS_P2P 0.0 17.9 55 55
AUTO_TS_P2F 0.0 8.3 40 40
AUTO_TS_F2P 0.0 11.7 15 15


Constraint: TS1000

Description: PERIOD:PERIOD_i1_A1:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_i2_CS:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_i3_RW:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_i9_RESET:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
i1_A1 to o15_DRQA 0.000 17.900 -17.900
i1_A1 to o17_IORD 0.000 17.900 -17.900
i1_A1 to o18_IOWR 0.000 17.900 -17.900


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
data_in<0> to data_out<0>.D 0.000 8.300 -8.300
data_in<1> to data_out<1>.D 0.000 8.300 -8.300
data_in<2> to data_out<2>.D 0.000 8.300 -8.300


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
data_out<5>.Q to o17_IORD 0.000 11.700 -11.700
data_out<5>.Q to o18_IOWR 0.000 11.700 -11.700
data_out<6>.Q to o17_IORD 0.000 11.700 -11.700



Number of constraints not met: 3

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
i1_A1 71.429 Limited by Clock Pulse Width for i1_A1
i2_CS 71.429 Limited by Clock Pulse Width for i2_CS
i3_RW 71.429 Limited by Clock Pulse Width for i3_RW
i9_RESET 71.429 Limited by Clock Pulse Width for i9_RESET

Setup/Hold Times for Clocks

Setup/Hold Times for Clock i1_A1
Source Pad Setup to clk (edge) Hold to clk (edge)
data_in<0> 2.100 1.400
data_in<1> 2.100 1.400
data_in<2> 2.100 1.400
data_in<3> 2.100 1.400
data_in<4> 2.100 1.400
data_in<5> 2.100 1.400
data_in<6> 2.100 1.400
data_in<7> 2.100 1.400

Setup/Hold Times for Clock i2_CS
Source Pad Setup to clk (edge) Hold to clk (edge)
data_in<0> 2.100 1.400
data_in<1> 2.100 1.400
data_in<2> 2.100 1.400
data_in<3> 2.100 1.400
data_in<4> 2.100 1.400
data_in<5> 2.100 1.400
data_in<6> 2.100 1.400
data_in<7> 2.100 1.400

Setup/Hold Times for Clock i3_RW
Source Pad Setup to clk (edge) Hold to clk (edge)
data_in<0> 2.100 1.400
data_in<1> 2.100 1.400
data_in<2> 2.100 1.400
data_in<3> 2.100 1.400
data_in<4> 2.100 1.400
data_in<5> 2.100 1.400
data_in<6> 2.100 1.400
data_in<7> 2.100 1.400

Setup/Hold Times for Clock i9_RESET
Source Pad Setup to clk (edge) Hold to clk (edge)
data_in<0> 2.100 1.400
data_in<1> 2.100 1.400
data_in<2> 2.100 1.400
data_in<3> 2.100 1.400
data_in<4> 2.100 1.400
data_in<5> 2.100 1.400
data_in<6> 2.100 1.400
data_in<7> 2.100 1.400


Clock to Pad Timing

Clock i1_A1 to Pad
Destination Pad Clock (edge) to Pad
o15_DRQA 17.900
o17_IORD 17.900
o18_IOWR 17.900
data_out<0> 10.200
data_out<1> 10.200
data_out<2> 10.200
data_out<3> 10.200
data_out<4> 10.200
data_out<5> 10.200
data_out<6> 10.200
data_out<7> 10.200

Clock i2_CS to Pad
Destination Pad Clock (edge) to Pad
o15_DRQA 17.900
o17_IORD 17.900
o18_IOWR 17.900
data_out<0> 10.200
data_out<1> 10.200
data_out<2> 10.200
data_out<3> 10.200
data_out<4> 10.200
data_out<5> 10.200
data_out<6> 10.200
data_out<7> 10.200

Clock i3_RW to Pad
Destination Pad Clock (edge) to Pad
o15_DRQA 17.900
o17_IORD 17.900
o18_IOWR 17.900
data_out<0> 10.200
data_out<1> 10.200
data_out<2> 10.200
data_out<3> 10.200
data_out<4> 10.200
data_out<5> 10.200
data_out<6> 10.200
data_out<7> 10.200

Clock i9_RESET to Pad
Destination Pad Clock (edge) to Pad
o15_DRQA 17.900
o17_IORD 17.900
o18_IOWR 17.900
data_out<0> 10.200
data_out<1> 10.200
data_out<2> 10.200
data_out<3> 10.200
data_out<4> 10.200
data_out<5> 10.200
data_out<6> 10.200
data_out<7> 10.200


Clock to Setup Times for Clocks


Pad to Pad List

Source Pad Destination Pad Delay
i1_A1 o17_IORD 10.000
i1_A1 o18_IOWR 10.000
i2_CS o17_IORD 10.000
i2_CS o18_IOWR 10.000
i3_RW o17_IORD 10.000
i3_RW o18_IOWR 10.000
i4_ACK o15_DRQA 10.000
i4_ACK o17_IORD 10.000
i4_ACK o18_IOWR 10.000
i5_INTRQ o13_IRQA 10.000
i8_INPACK o15_DRQA 10.000



Number of paths analyzed: 110
Number of Timing errors: 110
Analysis Completed: Thu Jul 30 16:56:57 2020